1. Technical Field
This disclosure relates generally to processes for automatically compiling and optimizing control logic for high performance digital integrated circuits, and more particularly to a method for automatically compiling high performance control logic implemented using self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques.
2. Description of the Related Art
Integrated circuits may be designed to provide logic structures forming self-resetting complementary metal oxide semiconductor (SRCMOS) circuits, as described in U.S. Pat. No. 4,845,677 to Chappell et al., entitled "Pipelined Memory Chip Structure Having Improved Access Time"; in Chappell et al., "A 2-ns Cycle Time 3.8 ns Access 512-kb CMOSECL SRAM With a Fully Pipelined Architecture", IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 26, NO. 11, November 1991; and in U.S. Pat. No. 5,576,644, each of which are incorporated herein by reference.
SRCMOS may be used to implement SRCMOS Logic Array Macros (SLAMs), such as described in commonly assigned U.S. patent applications entitled "COMPILED SELF-RESETTING CMOS LOGIC ARRAY MACROS" and "A METHOD AND APPARATUS FOR GENERATING BIT-SLICE MACROS", which are being filed concurrently with this application, and which are incorporated herein by reference.
In fabricating high performance integrated circuits or chips to implement such SLAMs, a hierarchical design process is typically followed, in which a chip is divided into units, which are then further subdivided into macros, which are defined herein as subdivisions of a unit of a chip or integrated circuit (IC). Each macro is then implemented using a particular design and layout strategy. Some distinction is usually made between datapath macros, which process data, and control logic macros, which control the operations that are performed on the data.
Datapaths usually employ very regular structures which are repeated many times. In the current state of the art of high performance microprocessor design, the datapaths are usually designed using full-custom design styles, such as described in Este and Eshraghian, "Principles of CMOS VLSI Design", ADDISON WESLEY, 1991. Such full-custom design styles typically require that the definition of the logic be fairly complete before the design activity may proceed, which is an acceptable condition for datapath elements having well known and fairly standard interfaces. Also, by following this highly customized design style, one can achieve high performance for the datapath elements.
Designing and laying out control logic is very different from designing and laying out datapath elements. Since the speed at which datapath elements may run is determined by the speed of the logic which controls them, it is imperative that control logic also be designed to work at such high speeds. The specifications of the control logic tend to change throughout the design process, which accordingly requires fast turn-around in design, implementation, and testing. As described in L. Stok et al., "Booledozer: Logic Synthesis for ASICs", IBM JOURNAL OF RESEARCH AND DEVELOPMENT, VOL. 40, NO. 4, pp. 407-430; current state of the art techniques implement logic synthesis based on standard cells, which provides relatively fast turn-around, but typically does not support the performance that may be achieved in datapaths using dynamic circuitry, and in particular, SRCMOS circuitry.
Although a customized design style for control circuits results in improved control circuits with good performance, such a customized design style is not desirable due to the long turn-around time. Therefore, a need exists for a method and structures which facilitate quick design and implementation turn-around of control circuits while providing performance comparable to a full-custom design style.